Statement of the Problem
Conventional semiconductor devices typically comprise a semiconductor substrate, usually of doped monocrystalline silicon, and a plurality of sequentially formed intermetal dielectric layers and electrically conductive patterns. An integrated circuit contains a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Typically, the conductive patterns of vertically spaced metallization levels are electrically interconnected by vertically oriented conductive plugs filling via holes formed in the intermetal dielectric layer separating the metallization levels, while other conductive plugs filling contact holes establish electrical contact with active device regions, such as a source/drain region of a transistor, formed in or on a semiconductor substrate. Conductive lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type according to current technology may comprise five or more levels of metallization to satisfy device geometry and microminiaturization requirements.
As the density of integrated circuits increases and feature sizes become smaller, resistance-capacitance (RC) coupling and resulting RC delays become more of a problem. Since capacitance is directly proportional to the dielectric constant (“k”), RC problems can be reduced if a low-dielectric-constant material is used as insulating material.
Formation of integrated circuit elements, for example, memory cells, electrically-conductive interconnects, and wiring layers, typically includes patterning and etching of an integrated circuit substrate. These processes typically include deposition of an etch stop layer, patterning of the etch stop layer, then removal of portions of the etch stop layer, and subsequent etching of the substrate around the remaining portions of the etch stop layer. In a copper damascene process scheme, the remaining portions of an etch stop layer are not removed after etching. Instead, the remaining portions of the etch stop layer are included in the finished integrated circuit. If portions of an etch stop layer are included in a finished integrated circuit, it is important that the etch stop layer have a dielectric constant comparable to the low dielectric constant of insulators used in the integrated circuit. An etch stop layer having a dielectric constant higher than the insulating material proximate to it increases the overall dielectric constant. It is also important that an etch stop layer allow high selectivity during the etching process so that the layer above the etch stop layer that needs to be etched can be selectively etched.
Etch stop layers comprising silicon nitride (“SiN”) or silicon carbide (“SiC”) are being used in copper (“Cu”) damascene techniques. SiN and SiC layers possess good electrical properties and are good Cu-diffusion barriers and etch stop layers. Nevertheless, existing etch stop/barrier layers have a relatively high dielectric constant, k. For example, SiN has a dielectric constant of about 7, and SiC formed using tetramethylsilane (“4MS”) typically has a k-value in the range of about 4.3 to 5.5. Used as etch stop layers, materials having relatively high k-values inhibit desired reduction of the effective k of the overall damascene structure.